When metal wirings of semiconductors are formed, an electrical insulating material (for example, silicon oxide) is filled between the metal wirings to provide electrical insulation between the electrical paths formed by the metal wirings.
Fluorine-doped silicon oxide is characterized by reducing signal delay, compared to other silicon oxides without fluorine. Fluorine-doped silicon oxide has a lower dielectric constant (k) than other silicon oxides, and may be used as an interlayer insulating material in devices with small design rules. However, since fluorine has high diffusivity, fluorine in the silicon oxide layer may react with an OH radical included in tetra-ethyl-ortho-silicate (TEOS)-based oxide in a capping layer formed under metal wirings, thereby forming highly corrosive HF. HF may create undesirable bubbles or corrode metal. When HF is used to form a specific pattern, fluorine atoms in the HF may react with an OH radical included in the TEOS-based oxide to form strong HF, again creating bubbles and corroding metal.
Reference will now be made in detail to FIGS. 1A to 1C which are sectional views illustrating a method for manufacturing a semiconductor device.
A lower insulating layer 10 is formed over a semiconductor substrate 5 and a lower wiring 12 is formed over the lower insulating layer 10. An etch stop layer 15 and a low-k dielectric layer 17 are sequentially formed over the lower insulating layer 10 including the lower wiring 12. The etch stop layer 15 is formed of a silicon nitride layer and the low-k dielectric layer 17 may be formed of a single silicon oxide layer containing fluorine, for example a fluorine-doped SiOF layer, to improve the operating speed of the semiconductor device. A protective capping layer 20 is formed over the low-k dielectric layer 17 since subsequent processes may damage the low-k dielectric layer 17 and degrade its characteristics.
The capping layer 20 may be formed of a tetra-ethyl-ortho-silicate (TEOS) layer. A mask layer is formed over the capping layer 20 and is then patterned to form a mask pattern 23. The mask pattern 23 may be formed of a photoresist layer.
As shown in FIG. 1B, the capping layer 20 and the low-k dielectric layer 17 are sequentially dry-etched using the mask pattern 23 as an etch mask. This dry etching forms a preliminary via hole 25 through which the etch stop layer 15 over the lower wiring 12 is exposed. Gas containing fluorine atoms (e.g. CxFy and/or CHxFy) is used for dry etching. Fluorine atoms may enter the low-k dielectric layer 17 from the gas etchant since the low-k dielectric layer 17 has a porous, spongy structure.
As shown in FIG. 1C, a sacrifice layer 30 is formed over the semiconductor substrate, filling in preliminary via hole 25. A photoresist pattern 32 is then formed over the sacrifice layer 30. The sacrifice layer 30 is has a high wet etching selection ratio to the low-k dielectric layer 17. The sacrifice layer 30 is formed to prevent the profile of the preliminary via hole 25 from being deformed in subsequent processes. The sacrifice layer 30 may be formed of an organosiloxane or hydro-silses-quioxane (HSQ) layer containing hydrogen. H or H2O may enter the low-k dielectric layer 17 during the process of forming the sacrifice layer 30.
Hydrogen atoms may react with fluorine atoms that are already present in the low-k dielectric layer 17 during the dry etching or fluorine atoms in the low-k dielectric layer 17 may be diffused into the capping layer 20 and then react with an OH radical in the capping layer 20 to form HF. The silicon oxide-based low-k dielectric layer 17 may be dissolved by this HF to cause a void “A” or may be diffused into the lower wiring 12 to corrode the lower wiring 12.